1. Field
Exemplary embodiments of the present invention relate to a complementary metal oxide semiconductor (CMOS) image sensor, and more particularly, to a counting device for reducing a power consumption of a counter in a CMOS image sensor having a column parallel structure using a binning mode and a method therefor.
2. Description of the Related Art
In a conventional CMOS image sensor, regardless of column status, a counter array operation was simultaneously performed during a binning mode for summing a charge of neighboring pixels in a read-out operation. Thus, a column, which is not used in a binning mode, wastes an unnecessary power.
For example, since a CMOS image sensor having a column parallel structure using a single slope analog-digital converter (ADC) has a column, which is not used in the binning mode operation, unnecessary power consumption may occur from the column, which is not used in the binning mode operation.
Moreover, a counter clock speed increases during 2×2 or 3×3 binning mode operation. A power consumption, which is caused by the increase of the counter clock speed, may cause a supply voltage drop as much as I2×R, where I denotes a current, and R denotes a resistance. Thus, a stable circuit operation may be stopped.